Sökning: "jasper gold"

Hittade 3 uppsatser innehållade orden jasper gold.

  1. 1. Omvänd skattskyldighet - En ”quick fix” för mervärdesskattebedrägerier?

    Kandidat-uppsats, Lunds universitet/Juridiska institutionen; Lunds universitet/Juridiska fakulteten

    Författare :Jasper Zimmerling; [2023]
    Nyckelord :skatterätt; finansrätt; rättsekonomi; EU-rätt; Law and Political Science;

    Sammanfattning : Every year, the members of the European Union lose tens of billions of euros in VAT revenue. A large part of these losses are due to widespread fraud that exploits the laws and rules governing intra-EU trade between EU Member States. One such fraud is Missing Trader Intra Community (MTIC) fraud. LÄS MER

  3. 2. What are the main drivers of gold price?

    Kandidat-uppsats, KTH/Matematisk statistik

    Författare :Jasper Wijk; Per Hidmark; [2023]
    Nyckelord :Regression analysis; Gold price; Oil Price; TIPS; DXY; CPI; S P 500; Regressionsanalys; Guldpris; Oljepris; TIPS; DXY; CPI; S P 500;

    Sammanfattning : This research paper revolves around the world’s oldest financial asset, gold, and whatdrives its price, which is of importance for all investors looking to be exposed to gold.The aim of this paper is to identify the main drivers behind the gold price, whichis done by performing a multiple linear regression analysis on the gold price and aset of explanatory variables. LÄS MER

  4. 3. Validation of efficiency of formal verification methodology for verification closure

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Gautham Prabhakar; [2022]
    Nyckelord :UVM; formal verification; assertions; verification engineers; SVA; TLV; jasper gold; UVM; formell verifiering; assertions; verifierar; SVA; TLV; jasper gold;

    Sammanfattning : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. LÄS MER