Sökning: "All-digital Phase-locked-loops"

Hittade 2 uppsatser innehållade orden All-digital Phase-locked-loops.

1. 1. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Simon Richter; [2023]
   Nyckelord :Phase-locked-loops; All-digital Phase-locked-loops; Time-to-digital converters; 5G and beyond; Radio-frequency design; Fas-låsd-loop; Helt-digital fas-låst-loop; Tid-till-digital-omvandlare; 5G och framtiden; Radio-frekvens design;

   Sammanfattning : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. LÄS MER

3. 2. Multi-Path Dierential Delay Line based Time-to-Digital Converter for ADPLL

   Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)

   Författare :XIAOLONG CHEN; [2013]
   Nyckelord :;

   Sammanfattning : All digital phase-locked loops (ADPLLs) play an important role in contemporary applications such as Bluetooth, GSM, WCDAM and WiFi. A timeto-digital converter (TDC) is the critical part in the ADPLL, usually the dominant quantization noise contributor. The quantization noise is caused by the nite resolution of the TDC. LÄS MER