Sökning: "Phase-locked-loops"

Visar resultat 1 - 5 av 7 uppsatser innehållade ordet Phase-locked-loops.

1. 1. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Simon Richter; [2023]
   Nyckelord :Phase-locked-loops; All-digital Phase-locked-loops; Time-to-digital converters; 5G and beyond; Radio-frequency design; Fas-låsd-loop; Helt-digital fas-låst-loop; Tid-till-digital-omvandlare; 5G och framtiden; Radio-frekvens design;

   Sammanfattning : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. LÄS MER

3. 2. Vicinity Integrated Circuit Card Emulation of ISO15693 in NFC Devices

   Master-uppsats, Uppsala universitet/Institutionen för informationsteknologi

   Författare :Elmar Xander van Rijnswou; [2018]
   Nyckelord :;

   Sammanfattning : This thesis describes the work flow of integrating a new digital design in an existing integrated circuit, the SN100V designed by NXP. The new digital design enables theSN100V for emulating ISO 15693 card, which is not available yet in any near field radio device. LÄS MER

4. 3. Phase Locked Loops in Fully Integrated NB-IoT Transceivers

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Adam Waks; [2018]
   Nyckelord :Phase locked loops; Narrow Band Internet of Things; Frequency pulling; Balun; Inductor; Technology and Engineering;

   Sammanfattning : This thesis investigates how to fulfill the Narrow Band - Internet of Things (NB-IoT) specification for a fully integrated transceiver in the phase locked loop's (PLL) perspective. Designing a fully integrated transceiver, integrating a power amplifier (PA) is challenging as it leads to frequency pulling of the voltage controlled oscillator (VCO) in the PLL, deteriorating the performance. LÄS MER

5. 4. Multi-Path Dierential Delay Line based Time-to-Digital Converter for ADPLL

   Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)

   Författare :XIAOLONG CHEN; [2013]
   Nyckelord :;

   Sammanfattning : All digital phase-locked loops (ADPLLs) play an important role in contemporary applications such as Bluetooth, GSM, WCDAM and WiFi. A timeto-digital converter (TDC) is the critical part in the ADPLL, usually the dominant quantization noise contributor. The quantization noise is caused by the nite resolution of the TDC. LÄS MER

7. 5. Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops

   Uppsats för yrkesexamina på grundnivå, Institutionen för teknik och naturvetenskap

   Författare :Robert Eklund; [2005]
   Nyckelord :PLL; VCXO; modulation bandwidth; tuning sensitivity correction;

   Sammanfattning : This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. LÄS MER