Sökning: "instruction scheduling"

Visar resultat 1 - 5 av 20 uppsatser innehållade orden instruction scheduling.

1. 1. Optimizing the instruction scheduler of high-level synthesis tool

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Zihao Xu; [2023]
   Nyckelord :Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

   Sammanfattning : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). LÄS MER

3. 2. Machine Learning-Based Instruction Scheduling for a DSP Architecture Compiler : Instruction Scheduling using Deep Reinforcement Learning and Graph Convolutional Networks

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Lucas Alava Peña; [2023]
   Nyckelord :Instruction Scheduling; Deep reinforcement Learning; Compilers; Graph Convolutional Networks; Schemaläggning av instruktioner; Deep Reinforcement Learning; kompilatorer; grafkonvolutionella nätverk;

   Sammanfattning : Instruction Scheduling is a back-end compiler optimisation technique that can provide significant performance gains. It refers to ordering instructions in a particular order to reduce latency for processors with instruction-level parallelism. LÄS MER

4. 3. Multifunktionellt verktyg för bockning och stansning

   Uppsats för yrkesexamina på grundnivå, Uppsala universitet/Industriell teknik

   Författare :Tua Martinsson; Hedda Thunell; [2023]
   Nyckelord :Punching; Bending; Additive Manufacturing; Product Development; Specification; Instruction Manual; Cutting Processes; Multifunctional; Tool; Pillar Press; Stansning; Bockning; Additiv tillverkning; Produktutveckling; Kravspecifikation; Instruktionsblad; skärande bearbetning; multifunktionell; Verktyg; Pelarpress;

   Sammanfattning : In general, bending and punching machines are large-scale equipment commonly used in factories or industries for mass production purposes. In this project, the opportunity to develop a smaller-scale multifunctional tool that can perform the same functions through manual force is investigated. LÄS MER

5. 4. The Global Interconnection Scheme of Silago : RTL Design and Verification

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Tong Lou; [2023]
   Nyckelord :Silago; global interconnection; synchronous dataflow; network on chip; Silago; global sammankoppling; synkront dataflöde; nätverk på chip;

   Sammanfattning : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. LÄS MER

7. 5. Register Caching for Energy Efficient GPGPU Tensor Core Computing

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Qiran Qian; [2023]
   Nyckelord :Computer Architecture; GPGPU; Tensor Core; GEMM; Energy Efficiency; Register File; Cache; Instruction Scheduling; Datorarkitektur; GPGPU; Tensor Core; GEMM; energieffektivitet; registerfil; cache; instruktionsschemaläggning;

   Sammanfattning : The General-Purpose GPU (GPGPU) has emerged as the predominant computing device for extensive parallel workloads in the fields of Artificial Intelligence (AI) and Scientific Computing, primarily owing to its adoption of the Single Instruction Multiple Thread architecture, which not only provides a wealth of thread context but also effectively hide the latencies exposed in the single threads executions. As computational demands have evolved, modern GPGPUs have incorporated specialized matrix engines, e. LÄS MER