DLL Based Reference Multiplier for the use in a PLL for WLAN applications

Sammanfattning: This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. To lock the DLL, input signal is required to be delayed only for three by eighth of the period of input reference signal. The linear tuning range of the inverter-based voltage control delay line (VCDL) has been extended by making minimal modification in the circuit. Introduced VCDL shows good phase noise performance as less number of delay units are used due to wider delay range. The effect of reference multiplier’s jitter and spurs on the PLL’s performance has been analyzed. The circuit has been implemented in 55 nm CMOS technology from Global Foundry. For 160 MHz output signal, simulated results show an average of 4.5 dBc/Hz improvement in phase noise throughout the offset frequencies with the output jitter of 6 ps and dynamic current consumption of 2.767 mA