Sökning: "Cilk"
Visar resultat 1 - 5 av 6 uppsatser innehållade ordet Cilk.
1. Parallelization in Rust with fork-join and friends: Creating the fork-join framework
H-uppsats,Sammanfattning : This thesis describes the design, implementation and benchmarking of a work stealing fork-join library, called ForkJoin, for the new language Rust. Rust is a programming language with a novel approach to memory safety and concurrency, and guarantees memory safety through zero-cost abstractions and thorough checks at compile time rather than run time. LÄS MER
2. Modeling Intel® Cilk™ Plus Programs with Unified Modeling Languages
Kandidat-uppsats, Linnéuniversitetet/Institutionen för datavetenskap (DV)Sammanfattning : Recently multi-core processors have become very popular in computer systems. It allows multiple threads to be executed simultaneously. The advantage of multi-core comes by parallelizing codes to expand the work across hardware. Furthermore, this can be done by using a parallel environment developed by M. LÄS MER
3. Porting Cilk to the Barrelfish OS
Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)Sammanfattning : Barrelfish operating system is an experimental instance of multikernel structure which exhibits good features such as hardware heterogeneity, scalability, dynamicity, etc. Barrelfish is in progress and lacks applications. LÄS MER
4. A Comparison of Different Parallel Programming Models for Multicore Processors
Uppsats för yrkesexamina på avancerad nivå, KTH/Skolan för informations- och kommunikationsteknik (ICT)Sammanfattning : As computers are used in most areas today improving their performance is of great importance. Until recently a faster processor was the main contributor to the increase of overall computer speed. Today the situation has changed as heating is becoming a bigger problem. LÄS MER
5. Exploiting locality in OpenMP task scheduling
Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)Sammanfattning : Future multi- and many- core processors are likely to have tens of cores arranged in a tiled architecture where each tile will house a processing core and a bank of the shared last-level cache. The physical distribution of tiles on the processor die gives rise to a Distributed Shared Cache (DSC) architecture where cache access latencies are non-uniform and depend on the physical distance between core and cache bank. LÄS MER