Sökning: "Compiler Architecture"
Visar resultat 1 - 5 av 46 uppsatser innehållade orden Compiler Architecture.
1. Machine Learning-Based Instruction Scheduling for a DSP Architecture Compiler : Instruction Scheduling using Deep Reinforcement Learning and Graph Convolutional Networks
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : Instruction Scheduling is a back-end compiler optimisation technique that can provide significant performance gains. It refers to ordering instructions in a particular order to reduce latency for processors with instruction-level parallelism. LÄS MER
2. Parallel Query Systems : Demand-Driven Incremental Compilers
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : Query systems were recently introduced as an architecture for constructing compilers, and have shown to enable fast and efficient incremental compilation, where results from previous builds is reused to accelerate future builds. With this architecture, a compiler is composed of several queries, each of which extracts a small piece of information about the source program. LÄS MER
3. Prototyping an mcSAT-based SMTsolver in Rust
Master-uppsats, Uppsala universitet/Institutionen för informationsteknologiSammanfattning : Satisfiability modulo theories, or SMT, is the decision problem of determining whether a set of formulas is satisfiable or not, given one or more background theories. The model-constructing satisfiability calculus, or mcSAT, is a framework used for solving SMT problems. LÄS MER
4. VM Instruction Decoding Using C Unions in Stack and Register Architectures
Kandidat-uppsats, Malmö universitet/Institutionen för datavetenskap och medieteknik (DVMT)Sammanfattning : The architecture of virtual machine (VM) interpreters has long been a subject of researchand discussion. The initial trend of stack-based interpreters was shortly thereafterchallenged by research showing the performance advantages of virtual register machines. LÄS MER
5. Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. LÄS MER