Sökning: "Hardware Verification"

Visar resultat 6 - 10 av 114 uppsatser innehållade orden Hardware Verification.

  1. 6. The Global Interconnection Scheme of Silago : RTL Design and Verification

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Tong Lou; [2023]
    Nyckelord :Silago; global interconnection; synchronous dataflow; network on chip; Silago; global sammankoppling; synkront dataflöde; nätverk på chip;

    Sammanfattning : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. LÄS MER

  3. 7. Modularity, Scalability, Reusability, Configurability, and Interoperability of ASIC/FPGA Verification IP

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Trupti Rao; [2022]
    Nyckelord :Verification Intellectual Property; UniversalVerification Methodology; Avalon Streaming Interface; Object-oriented Programming;

    Sammanfattning : The complexity of chip design has been exponentially rising, resulting in increased complexity and costs in chip verification. This rise in complexity results in increased time to market and increases risks of chip in fabrication, that can be catastrophic and result in major losses. LÄS MER

  4. 8. Investigating Machine Learning for verification of AMBA APB protocol.

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Abhiram Srisai Kishore; Mohammed Wasim; [2022]
    Nyckelord :Machine learning; SOC Verification; AMBA; Neural Networks; Deep Learning; Assertions.; Technology and Engineering;

    Sammanfattning : It is a well-known fact that in any Application Specific Integrated Circuit (ASIC) design, verification consumes most time and resources. And when it comes to huge designs, finding bugs can be tedious given the area and the complexity. As per Moore’s law, the design complexity is increasing exponentially due to the growing demand for performance. LÄS MER

  5. 9. RAUK: Automatic Schedulability Analysis of RTIC Applications Using Symbolic Execution

    Uppsats för yrkesexamina på avancerad nivå, Luleå tekniska universitet/Institutionen för system- och rymdteknik

    Författare :Mark Håkansson; [2022]
    Nyckelord :RTIC; symbolic execution; embedded systems; software verification; software analysis; schedulability;

    Sammanfattning : In this thesis, the proof-of-concept tool RAUK for automatically analyzing RTIC applications for schedulability using symbolic execution is presented. The RTIC framework provides a declarative executable model for building embedded applications, which behavior is based on established formal methods and policies. LÄS MER

  7. 10. Application of formal verification and validation on modern multi-functional signalling system

    Master-uppsats, KTH/Transportplanering

    Författare :Shamsul Arefin; [2022]
    Nyckelord :;

    Sammanfattning : Demand for rail transport is increasing day by day. Rail is popular in public transport due to punctuality, regularity, and safety. However, we hear daily that rail traffic still has many problems to solve about incidents, near misses, and signal errors. LÄS MER