Sökning: "FinFET"

Visar resultat 1 - 5 av 11 uppsatser innehållade ordet FinFET.

  1. 1. Design and Modeling of InxGa(1−x)As/InP based Nanosheet Field Effect Transistors for High Frequency Applications

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Hanyu Liu; Xi Chen; [2023]
    Nyckelord :nanosheet NS ; gate-all-around GAA ; channel release; parasitic channel; MATLAB; COMSOL; technology node; Technology and Engineering;

    Sammanfattning : The advancement of CMOS technology has been fueled by the need to satisfy Moore’s law by shrinking transistors to progressively smaller sizes and increasing the transistor density per unit area [1]. The dimension of the state-of-the-art MOSFET is now down to a few nanometers. LÄS MER

  2. 2. A Simulation Study of Variability in Gate-all-Around Nanosheet Transistors

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Virinchi Tirumaladass; [2022]
    Nyckelord :Gate-all-around; Nanosheet field effect transistors; process variations; variability; TCAD; Gate-all-around; Nanoblad fälteffekttransistorer; processvariationer; variabilitet; TCAD;

    Sammanfattning : Gate-all-around (GAA) nanosheet field effect transistors (NSFETs) seem to be one of the most promising replacement options for FinFETs towards scaling down below to the sub-7nm technology nodes. They offer better electrostatics and control of short channel effects (SCEs) due to their superior control over the channel and their large effective channel width. LÄS MER

  3. 3. Investigation on the Optimization of GaN Etching for FinFET Applications

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Albert Malmros; [2022]
    Nyckelord :Technology and Engineering;

    Sammanfattning : In the framework of this thesis, the optimization of the etching process of GaN for FinFET applications has been investigated. FinFETs are transistors with a vertical architecture in the shape of fins. These fins are fabricated by etching a pattern into a GaN substrate. The etching is carried out in two steps, a dry etch and a wet etch. LÄS MER

  4. 4. Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Limitha Subbaiah Kumar Nangaru; [2022]
    Nyckelord :CMOS Complementary Metal Oxide Semiconductors ; DRC Design Rule Check ; Process Corners; FinFET Fin Field Effect Transistor ; IC Integrated Circuit ; LVS Layout Versus Schematic ; Monte Carlo; Nominal Voltage; PDK Process Design Kit ; Power Delay Product; Read Bit Line; Read Word Line; SoC System on Chip ; SRAM Static Random Access Memory ; Threshold Voltage; Technology and Engineering;

    Sammanfattning : System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. LÄS MER

  5. 5. Low power memory controller subsystem IP exploration using RTL power flow : An End-to-end power analysis and reduction Methodology

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Neerajnayan Balachandran; [2020]
    Nyckelord :Power analysis; Block characterization; Optimization; Differential Energy analysis; Dynamic Power; Clock gating.; Power-analys; Block karakterisering; Optimering; Differential Energy-analys; Dynamic Power; Clock gating;

    Sammanfattning : With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. LÄS MER