Sökning: "Instruction set architecture"

Visar resultat 1 - 5 av 34 uppsatser innehållade orden Instruction set architecture.

1. 1. RVSingle: A general purpose power efficient RISC-V for FPGAs

   Master-uppsats, Linköpings universitet/Elektroniska Kretsar och System

   Författare :YuYang Shen; [2023]
   Nyckelord :;

   Sammanfattning : With the increasing need for low-cost, power-efficient computing units, RISC-Vas an open-standard Instruction Set Architecture (ISA) is becoming more and more popular in the industry. There are multiple open-source RISC-V soft processors like cva6, VEGA, NOEL-V and more. LÄS MER

3. 2. Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Kristoffer Westring; Linus Svensson; [2023]
   Nyckelord :FPGA; ASIC; Near Memory Computing; RISC-V; Convolutional Neural Network; Technology and Engineering;

   Sammanfattning : The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. LÄS MER

4. 3. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Ziyan He; [2022]
   Nyckelord :RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

   Sammanfattning : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. LÄS MER

5. 4. A Benchmark and Evaluation of Imperas OVPSim Virtual Platform Tool Using RISC-V Processors

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Annan Liu; [2022]
   Nyckelord :;

   Sammanfattning : In recent years, there has been a rapid development of embedded processors. These processors are designed for domains like aerospace, automotive, automation, healthcare, and more. However, both hardware and software must be validated before the actual application. Manufacturing a processor requires extremely high cost and a long time to finish. LÄS MER

7. 5. Hybrid Debugger Software on RISC-V MCU : A no cost debugging solution foreducational use

   Kandidat-uppsats, KTH/Hälsoinformatik och logistik

   Författare :Linus Remahl; [2022]
   Nyckelord :RISC-V instruction set architecture; debugging; debug module; trigger module; remote serial protocol; micro controller unit; RISC-V instruktionsuppsättning; felsökning; debug module; trigger module; remote serial protocol; mikrokontroller;

   Sammanfattning : This work details the implementation of a debugger for a small embedded RISC-V system. KTH uses an in-house designed microcontroller development board for computer and electronics design courses. LÄS MER