Sökning: "ericsson asic"

Visar resultat 1 - 5 av 21 uppsatser innehållade orden ericsson asic.

  1. 1. Introducing Machine Learning in a Vectorized Digital Signal Processor

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Linnéa Ridderström; [2023]
    Nyckelord :Digital Signal Processor DSP ; Application-Specific Integrated Circuit ASIC ; Machine Learning; Deep Learning; Convolutional Neural Network CNN ; Very Long Instruction Word VLIM ; Single Instruction Multiple Data SIMD ; Digital Signalprocessor DSP ; Applikation-Specifik Integrerad Krets ASIC ; Maskininlärning; Djupinlärning; Konvolutionella Neurala Nätverk CNN ; Very Long Instruction Word VLIW ; Single Instruction Multiple Data SIMD ;

    Sammanfattning : Machine learning is rapidly being integrated into all areas of society, however, that puts a lot of pressure on resource costraint hardware such as embedded systems. The company Ericsson is gradually integrating machine learning based on neural networks, so-called deep learning, into their radio products. LÄS MER

  3. 2. Investigating Machine Learning for verification of AMBA APB protocol.

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Abhiram Srisai Kishore; Mohammed Wasim; [2022]
    Nyckelord :Machine learning; SOC Verification; AMBA; Neural Networks; Deep Learning; Assertions.; Technology and Engineering;

    Sammanfattning : It is a well-known fact that in any Application Specific Integrated Circuit (ASIC) design, verification consumes most time and resources. And when it comes to huge designs, finding bugs can be tedious given the area and the complexity. As per Moore’s law, the design complexity is increasing exponentially due to the growing demand for performance. LÄS MER

  4. 3. Design space exploration using HLS in relation to code structuring

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Debraj Das; [2022]
    Nyckelord :Design Space Exploration DSE ; High level Synthesis HLS ; Design Methodology;

    Sammanfattning : High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. LÄS MER

  5. 4. Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Zilin Zhang; [2021]
    Nyckelord :Technology and Engineering;

    Sammanfattning : Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For some EMCA IP blocks a hierarchical clock gating mechanism ensures coarse-grained power savings based on actual processing need but for many blocks this approach cannot be employed. LÄS MER

  7. 5. RTL power estimation and optimization flow for 5G radio products

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Divya Khanna; Yu Zhu; [2021]
    Nyckelord :Power estimation; RTL; gate-level; Power Optimisation; Technology and Engineering;

    Sammanfattning : Power reduction is becoming a critical design requirement for ASIC/SOC designers. Reducing both dynamic and leakage power is essential to meet power budgets for portable devices as well as to ensure that these ASICs meet their packaging and cooling costs. LÄS MER