Sökning: "System på chip"

Visar resultat 1 - 5 av 122 uppsatser innehållade orden System på chip.

1. 1. Deep Learning Model Deployment for Spaceborne Reconfigurable Hardware : A flexible acceleration approach

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Javier Ferre Martin; [2023]
   Nyckelord :Space Situational Awareness; Deep Learning; Convolutional Neural Networks; FieldProgrammable Gate Arrays; System-On-Chip; Computer Vision; Dynamic Partial Reconfiguration; High-Level Synthesis; Rymdsituationstänksamhet; Djupinlärning; Konvolutionsnätverk; Omkonfigurerbara Field-Programmable Gate Arrays FPGAs ; System-On-Chip SoC ; Datorseende; Dynamisk partiell omkonfigurering; Högnivåsyntes.;

   Sammanfattning : Space debris and space situational awareness (SSA) have become growing concerns for national security and the sustainability of space operations, where timely detection and tracking of space objects is critical in preventing collision events. Traditional computer-vision algorithms have been used extensively to solve detection and tracking problems in flight, but recently deep learning approaches have seen widespread adoption in non-space related applications for their high accuracy. LÄS MER

3. 2. Code Synthesis for Heterogeneous Platforms

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Zhouxiang Fu; [2023]
   Nyckelord :Code Synthesis; Heterogeneous Platform; Zero-Overhead Topology Infrastructure; Kodsyntes; Heterogen plattform; Zero-Overhead Topologi Infrastruktur;

   Sammanfattning : Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. LÄS MER

4. 3. Performance of 2-18 GHz RF Switches Implemented in Chip & Wire Technology : Analysis of switch topologies, bias networks and an in-depth EM analysis of bondwires

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Gustav Eliasson; [2023]
   Nyckelord :RF Switch; PIN diode; Chip Wire Technology; Wide Bandwidth; High isolation; Single-Pole-Single-Throw; Single-Pole-Double-Throw RF Switch; PIN diode; Chip Wire Technology; Wide Bandwidth; Single-Pole-SingleThrow; Single-Pole-Double-Throw; RF-omkopplare; PIN-diod; Chip Wire Tekonologi; Bredbandig; Hög isolation; Enkelpolig-enkakast; Enkelpolig-dubbelkast;

   Sammanfattning : The ability to control the path a signal takes through microwave circuitry is crucial when designing RF systems. The component that allows for the control of the signal path is called a switch, and it is the microwave component that this thesis will focus on. LÄS MER

5. 4. Positionering med hjälp av Ultra-Wideband : En delstudie för Sjöfartshögskolan i Kalmar

   M1-uppsats, Linnéuniversitetet/Sjöfartshögskolan (SJÖ)

   Författare :Peter Tullstedt; Richard Birgander; [2023]
   Nyckelord :Ultra Wideband; UWB; Positioning; Arduino; AOS; ESP32; BNO055;

   Sammanfattning : Sjöfartshögskolan i Kalmar har ett långtgående studentprojekt att bygga en modell av skolfartyget M/S Calmare Nyckel som autonomt ska köra runt i en damm på skolan för att visa upp skolans profil. Projektet är tänkt att sammanfoga kunskaper från många olika delar av utbildningen såsom elektronik, programmering, och stabilitet. LÄS MER

7. 5. Optimizing the instruction scheduler of high-level synthesis tool

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Zihao Xu; [2023]
   Nyckelord :Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

   Sammanfattning : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). LÄS MER